|
The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz.〔(ARM Cortex-A15 - ARM Processor )〕 ==Overview== (詳細はCortex-A9 core with the same number of cores at the same speed.〔(Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 )〕 The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012.〔 Key features of the Cortex-A15 core are: * 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.〔(ARM7 40-bit, virtualization )〕〔(ARM e-mail to LINUX: Add support for the Large Physical Address Extensions )〕 As per the x86 Physical Address Extension, virtual address space remains 32 bit.〔("Calxeda plots server dominance with ARM SoCs." )〕 * 15 stage integer/17–25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalar execution pipeline〔(Exploring the Design of the Cortex-A15 Processor ) Travis Lanier〕 * 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (CCI-400, an AMBA-4 coherent interconnect) and 4 clusters per chip with CCN-504.〔("ARM A15 web page, Specification tab" )〕 ARM provides specifications but the licencees individually design ARM chips, and AMBA-4 scales beyond 2 clusters. The theoretical limit is 16 clusters; 4 bits are used to code the CLUSTERID number in the CP15 register (bits 8 to 11).〔("Cortex-A15 MPCore Technical Reference Manual" )〕 * DSP and NEON SIMD extensions onboard (per core) * VFPv4 Floating Point Unit onboard (per core) * Hardware virtualization support * Thumb-2 instruction set encoding to reduce the size of programs with little impact on performance * TrustZone security extensions * Jazelle RCT for JIT compilation * Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution * 32 KB data + 32 KB instruction L1 cache per core * Integrated low-latency level-2 cache controller, up to 4 MB per cluster 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「ARM Cortex-A15」の詳細全文を読む スポンサード リンク
|